Electronic Logic Systems |
From inside the book
Results 1-3 of 20
Page 129
... Flip - Flop ( SR / FF ) = This device has two inputs , the set S and the reset R , as shown in Fig . 4.2 . When a logic 1 is applied to S , the flip - flop is set to 1 ( Q 1 ) . When a logic 1 is applied to R , the flip - flop is reset ...
... Flip - Flop ( SR / FF ) = This device has two inputs , the set S and the reset R , as shown in Fig . 4.2 . When a logic 1 is applied to S , the flip - flop is set to 1 ( Q 1 ) . When a logic 1 is applied to R , the flip - flop is reset ...
Page 130
... SR / FF can be implemented using NOR gates , as in Fig . 4.5 . R Q S Fig . 4.5 NOR implementation of an SR / FF From Fig . 4.5 , Q = S + Q Q = R + S + Q = R ( S + Q ) = RS + RQ = RS + RQ + RS since SR = 0 = S + RQ Up to now , the S and ...
... SR / FF can be implemented using NOR gates , as in Fig . 4.5 . R Q S Fig . 4.5 NOR implementation of an SR / FF From Fig . 4.5 , Q = S + Q Q = R + S + Q = R ( S + Q ) = RS + RQ = RS + RQ + RS since SR = 0 = S + RQ Up to now , the S and ...
Page 131
... SR / FF Master - Slave SR / FF Fig . 4.8 shows the construction of a master - slave SR / FF . To illustrate its operation consider the following condition : C = 0 , Q1 = 0 , Q2 = 0 If S is made 1 and R is made 0 , and the clock Cis kept ...
... SR / FF Master - Slave SR / FF Fig . 4.8 shows the construction of a master - slave SR / FF . To illustrate its operation consider the following condition : C = 0 , Q1 = 0 , Q2 = 0 If S is made 1 and R is made 0 , and the clock Cis kept ...
Contents
Exercises | 34 |
Chapter 3 Combinational Logic at Different Levels of Integration | 97 |
Chapter 4 Synchronous Sequential Circuits | 128 |
Copyright | |
8 other sections not shown
Other editions - View all
Common terms and phrases
2's complement ABCD assignment asynchronous asynchronous circuits B₁ binary numbers bits block diagram C₁ cell chip clock pulse closed partitions CMOS column combinational logic components control variables counter d₁ decimal decomposed decomposition digit diodes divisor Equation EX-OR f₁ flip-flop flow table four-bit full adder given groups implementation of Example input variables K-map logic circuits logic function logic gates minterms multiplication N₁ N₂ NAND gates nMOS number of inputs number of modules open collector output P₁ pairs parallel possible present primary inputs PRINT product terms R₁ read only memory residue matrix s.p. partitions S₁ sequential circuits sequential machine shift register shown in Fig shown in Table simplified SR/FF subtraction synchronous sequential T₁ T₂ technique three-variable transistor truth table voltage X₁ X₁X2 Y₁ Y₂